A number of functional units are utilized by a network processor to manage the flow of data. Among these are memory interfaces to provide memory arbitration; state machines to provide functionality of processing command messages; and receive, transmit and dispatch controllers, just to name a few. A memory interface attempts to provide buffer management and data movement at media speed. To eliminate the memory access bandwidth bottleneck, the main function of the memory interface is to provide an efficient memory access scheme while meeting the requirements of sustained data throughput at the required data rate at the memory controller interface to the memory device.
Network traffic management requires hardware implementation for scheduling the delivery of network packets, and for traffic shaping. For this, a computer employs a scheduler which is a computer program designed to perform advanced scheduling algorithms to control functions, such as network packet scheduling, traffic shaping, and initiation and termination of specified tasks. Hardware schedulers contain a plurality of network interface and switch ports, an internal memory for DRAM write access command queues as well as buffers for received packets, an internal memory for DRAM read access command queues and finite state machines for memory management. The system utilizes external SRAM and DRAM memory devices to store control blocks of scheduling elements. It is necessary to be able to quickly and accurately execute searches for programs with complex flow patterns.
A number of features are found in related art devices, but none of these devices embody the combination of features that are found in the present invention. For example, some conventional DRAM access arbiters consider only one access request across several memory banks at a time, thereby leading to low memory bandwidth utilization. Other DRAM access arbiters employ schemes to increase the memory access bandwidth, but access command queues are global queuing structures which contain access requests to all the memory banks of the memory device.
Neither of these schemes imposes any limitation on how many access requests for the same memory bank can be presented in the command queues. The command queues can be populated with access requests to the same memory bank. Command queues are limited resources, such that new access requests for different memory banks cannot be inserted into the command queues while these queues are full. This problem results in low memory bandwidth utilization for a period of time.
In some applications where a “cut-and-paste” processing model is used, the “paste” of a packet header also contributes to the write accesses traffic to the memory. In this case, flow control on the regular write access traffic is required in order to guarantee that the “paste” operation of packet data is given the highest priority to access the memory devices.